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This is the tick timer (TT), power management (PM), and programmable interrupt 
controller (PIC) synthesis project deliverables folder.  These are peripherals 
for the OR1200 open source processor.
By Elena Weinberg (ekw7ej@virginia.edu)
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*verilog* folder contains all the HDL needed for this project.

For Design Compiler:
or1200_tt.v 
or1200_pm.v
or1200_pic.v

For DFT:
or1200_tt_dft.v 
or1200_pm_dft.v
or1200_pic_dft.v

*netlist* folder contains synthesized netlists after DFT:
or1200_tt_dc.v
or1200_pm_dc.v
or1200_pic_dc.

*constraint* folder contains all constraint files.  
They are all called constr.sdc but are in their respective folders, TT, PM, and PIC.

*scripts* folder includes scripts I used in Design Compiler and IC Compiler

*sram1024x8* folder includes generated SRAM CEL and FRAM views not used in this project

